1. Field of the Invention
The present invention relates to flash memory device reliability and more particularly to flash memory write cycle bandwidth management.
2. Description of the Related Art
Flash memory refers to non-volatile computer readable storage medium that can be electrically erased and reprogrammed. Flash memory initially had been developed from electrically erasable programmable read-only memory and stores information in an array of memory cells made from floating-gate transistors. In traditional single-level cell devices, each cell of flash memory stores only one bit of information. Newer flash memory, known as multi-level cell devices, can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells.
Flash cells of a flash memory device can provide only a finite number of erase cycles. When the number of erases in the flash memory device exceeds this limit, the cell fails and eventually, the flash memory device fails. Flash memory devices are also capable of very high performance, which in effect, accelerates the end of life of the flash memory device. Flash memory devices also provide a warranty which guarantee reliable operation for a finite duration of time. Of note, it is well within the performance envelope to exceed the number of erase cycles of a flash memory device within the warranty period. Thus, in order to meet warranty requirements, flash memory devices may throttle write transactions. By slowing down the write transactions, the number of erase transactions is reduced, thus increasing the lifetime of the flash memory device.
In a virtual environment in which multiple virtual machines (VMs) execute in the physical memory of one or more computing systems, a single flash memory device may be shared by multiple VMs. So much is not a problem so long as the available write bandwidth of the flash memory device exceeds the bandwidth required by all of the VMs. However, as the available bandwidth of the flash memory decreases during write transaction throttling, a resource sharing issue can arise. Today, the limited write bandwidth of a flash memory device is not intelligently partitioned among the VMs. Instead, in a conventional VM-agnostic flash memory device controller, the write bandwidth remains a resource that is freely available to any VM demanding the write access to the flash memory device. This leads to a situation where the most aggressive VM is provided all or most of the available write bandwidth of the flash memory device, potentially leaving other VMs starving for access to the flash memory device.